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[VHDL-FPGA-Verilog] CANProtocolControllerIPCoreinVerilog

Description: 一种基于CAN协议的IP核源代码，用Verilog语言实现-CAN Protocol Controller IP Core in Verilog.
Platform: | Size: 67584 | Author: Nicholas | Hits:

[VHDL-FPGA-Verilog] xge_mac

Description: 10G MAC ip核源码其中包含了三个版本。经过测试正确无误。-======================== 10GE MAC Core ======================== ------------------------ 1. Directory Structure ------------------------ The directory structure for this project is shown below. . |-- doc - Documentation files | |-- rtl | |-- include - Verilog defines and utils | `-- verilog - Verilog source files for xge_mac | |-- sim | |-- systemc - SystemC simulation directory | `-- verilog - Verilog simulation directory | `-- tbench |-- systemc - SystemC test-bench source files `-- verilog - Verilog test-bench source files ------------------------ 2. Simulation ------------------------ There are two simulation environments that can be used to validate the code. The verilog simulation is very basic and meant for those who want to look at how the MAC operates without going through the effort of setting up SystemC. The SystemC environment is more sophisticated and covers
Platform: | Size: 899072 | Author: xuchao | Hits:

[Embeded-SCM Develop] ARMcore

Description: 基于FPGA的ARM IP核！该软核VHDL源码全部开放-FPGA-based ARM IP core! The soft core VHDL source code are all open
Platform: | Size: 690176 | Author: 王钊 | Hits:

[VHDL-FPGA-Verilog] quaddecoder_verilog_ise11.2_used_09042010

Description: Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File. The Pinout is descripted in the Constrained file quad.ucf. To use them, you need teh XC9536 and a clock source that s 4 times faster than the fastes signal that the incremental encoder can creates. IThe clock source frequency is uncritical. For manuel rotated incremental encoder like radio VFO oder other tuning knob, a simple TTL oscillator with about 1Mhz (i use 1.8432Mhz and tested 32768Khz) works brilliant. For very fast decoding, this core is not good enought because there are no Filter FlipFlops are programmed to suppress noises on the Channel A/B Lines.-Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File. The Pinout is descripted in the Constrained file quad.ucf. To use them, you need teh XC9536 and a clock source that s 4 times faster than the fastes signal that the incremental encoder can creates. IThe clock source frequency is uncritical. For manuel rotated incremental encoder like radio VFO oder other tuning knob, a simple TTL oscillator with about 1Mhz (i use 1.8432Mhz and tested 32768Khz) works brilliant. For very fast decoding, this core is not good enought because there are no Filter FlipFlops are programmed to suppress noises on the Channel A/B Lines.
Platform: | Size: 70656 | Author: JUPP | Hits:

[VHDL-FPGA-Verilog] 8051_latest.tar

Description: VHDL/VERILOG FOR 8051 Core
Platform: | Size: 7007232 | Author: mss | Hits:

[VHDL-FPGA-Verilog] can_latest.tar

Description: VHDL/VERILOG FOR CAN BUS Core
Platform: | Size: 1176576 | Author: mss | Hits:

[VHDL-FPGA-Verilog] sd_slave_device

Description: verilog source code for SD card SLAVE DEVICE IP-Core
Platform: | Size: 15360 | Author: Antti Lukats | Hits:

[VHDL-FPGA-Verilog] MyDDS

Description: 利用查找表法编写的DDS的verilog程序，节省了利用IP核实现需要的资源，软件为ISE，-Prepared using look-up table method of verilog DDS program, save the use of IP core implementation requires resources, software for the ISE,
Platform: | Size: 2891776 | Author: 蜡笔 | Hits:

[VHDL-FPGA-Verilog] cordic

Description: altera cordic ip core, 包含文档，完整设计，以及测试向量-altera coedic ip core, including the document, whole design, and the testbench.
Platform: | Size: 896000 | Author: panzhijian | Hits:

[VHDL-FPGA-Verilog] sdcard_mass_storage_controller_latest.tar

Description: 基于wishbone总线的SD Card IP Core,有Verilog和VHDL两种语言版本,包含了FIFO和DMA两种实现方式,是开源的IP Core-Based on the wishbone bus SD Card IP Core, there are two language versions of Verilog and VHDL, including the FIFO and DMA implemented in two ways, is open source IP Core
Platform: | Size: 2271232 | Author: 张亚群 | Hits:

[VHDL-FPGA-Verilog] arm6verilog

Description: arm6 verilog core very good 欢迎下载-arm6 verilog core
Platform: | Size: 7168 | Author: yzhang | Hits:

[VHDL-FPGA-Verilog] TERASIC_AUDIO

Description: 友晶提供的Audio的IP核。这个IP核提供了Verilog的硬件部分源码和相应的HAL驱动程序。-Audio provided by Friends of Crystal' s IP core. The IP core provides a Verilog hardware part of the source and the corresponding HAL driver.
Platform: | Size: 125952 | Author: changjiang | Hits:

[VHDL-FPGA-Verilog] pwm

Description: 利用Verilog语言产生17路PWM波，控制17路舵机，可以作为IP核添加到AVALON总线上，在nios IDE里用C语言控制。-Using Verilog language production of 17 Road PWM signal to control 17 Servos, can be used as IP core to the AVALON bus, in the nios IDE in control with the C language.
Platform: | Size: 3072 | Author: 尹长生 | Hits:

[VHDL-FPGA-Verilog] I2C_code

Description: 与IP核配套的I2C-Master Core，包含了目前主流FPGA芯片的I2C实现，代码包括Altera/Xilinx/OpenCore等公司的VHDL/Verilog/C等。-I2C-Master Core
Platform: | Size: 3256320 | Author: summerooooo | Hits:

[Com Port] i2c_latest.tar_1

Description: I2C的OPEN CORE 的代码，很使用，可以直接改参数-I2C open core ip。verilog
Platform: | Size: 1485824 | Author: chen | Hits:

[Other systems] lab8

Description: my labs on verilog. this is modeling of proccesor core
Platform: | Size: 5120 | Author: taranka | Hits:

[VHDL-FPGA-Verilog] IIC

Description: 用标准Verilog HDL 语言编写的IIC总线IP核，详细定义了时序及输入输出， 可以直接应用-Standard Verilog HDL language of the IIC bus IP core, a detailed definition of the timing and the input and output, can be applied directly
Platform: | Size: 3072 | Author: 吴梁辛 | Hits:

[VHDL-FPGA-Verilog] Floating-Point-Adder

Description: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.
Platform: | Size: 154624 | Author: 凌音 | Hits:

[VHDL-FPGA-Verilog] Cordic

Description: cordic算法ip核,国外网站搞到的,可以应用于电机控制，快速数值计算，基于FPGA硬件实现-cordic ip core,just enjoy
Platform: | Size: 241664 | Author: 刘业超 | Hits:

[VHDL-FPGA-Verilog] FPGA_FFT

Description: 基于IP核的FPGA FFT算法模块的设计与实现 在QUATUSII下实现-IP-based core module FPGA FFT algorithm design and implementation be achieved in QUATUSII
Platform: | Size: 222208 | Author: linxing | Hits:
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